1. Field of the Invention
The present disclosure relates to techniques for synchronizing operation of a circuit with a control signal.
The disclosure has been developed in view of the possible use for optimizing the latency of a synchronization system comprising a plurality of flip-flops.
2. Description of the Relevant Art
Complex electronic systems frequently envisage various hardware subsystems that operate in a concurrent way, each of which has a dedicated timing clock. In general, said clocks may not be correlated to one another; whence the term “concurrent asynchronous systems”.
There may, however, arise the need of linking the behaviour of any of these subsystems to the state of any other subsystem, in general of co-ordinating the evolution and the interaction of said processes so as to provide a perfectly predictable global behaviour.
It is thus necessary to tackle the problem of how to convey the information of synchronization from one clock domain to the other preventing said information from being erroneously interpreted. For this reason synchronization protocols are used, for example synchronization protocols of the “VALID” or “VALID/ACK” type, according to whether said communication is of a unidirectional type or of a bidirectional type.
For instance, FIG. 1 shows an example of a unidirectional synchronization, in which a system represented by a finite-state machine (FSM) FSM1 receives a control signal sync through a synchronization circuit 20.
For example, the circuit 20 may comprise a chain of registers (for example, flip-flops), in which the registers are driven with the clock signal CLK1 of the receiving system FSM1. In the example considered, the circuit 20 comprises two flip-flops 20a and 20b connected in series.
FIG. 2 shows, instead, an example of a bidirectional synchronization, in which two systems FSM1 and FSM2 exchange control signals through respective synchronization circuits.
In the example shown, the circuit FSM2 transmits to the circuit FSM1 through a synchronization circuit 20 a control signal VALID. In substantially the same way, the circuit FSM1 transmits to the circuit FSM2 through a synchronization circuit 22 a control signal ACK. This type of communication can be used, for example, to acknowledge proper reception of the signal VALID.
The number of flip-flops can be determined, for example, by the ratio between the operating frequency of the receiving system and the setup time of the particular type of flip-flop used so as to guarantee a complete immunity from the so-called phenomenon of metastability, which is typical in the case of signals that traverse different clock domains.
A “complete synchronization” of the above sort hence guarantees a unique determination of the value of the signal received, which may thus be used by the receiving machine.